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TDA7521
Analog Front End
PRODUCT PREVIEW
TDA7521 is a BiCMOS analog front end for CD applications. Four input signals (AC*, BD*, E* and F*), coming from the pick-up (whose laser diode is driven and controlled by the device itself), are preamplified by a programmable voltage-to-voltage or current-tovoltage stage, depending on the used pick-up. The output signals from the preamplifier stage (AC, BD, E, F and HF, a radio frequency signal obtained by combining the photo-detector outputs as A+B+C+D) are fed to an 8-bit HF ADC (for HF, which carries encoded audio data) and a 6-bit Servo ADC (for AC, BD, E and F, used for focusing, tracking the laser beam and controlling revolution speed). All these signals are digitized, multiplexed, synchronized with the external clock (768xFs or 394xFs, Fs=44.1KHz) and fed to the digital counterpart in one only digital stream (AC/HF/ BD/HF/E/HF/F/HF). Two stereo DACs convert the input bitstreams from TDA7522.
TQFP44 (10 x 10 x 1.40 mm body)
All the clock signals (for ADCs and DACs) are generated by a low-jitter PLL-based clock manager. All TDA7521's analog preprocessing is controlled by TDA7522 by means of an UART interface (which implex10mm package, TDA7521 features the functions ments an I2C-like protocol). Housed in a TQFP 44, 10 shown in figure below. TDA7521 uses the HF4CMOS technology and is supplied @5Vdc.
May 1998
This is preliminary information on a new product now in development. Details are subject to change without notice.
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Figure 1. TDA7521 Block Diagram
REXT
REF OUT
HF MON
FILT
REF IN PON
REF Gen
I/V
CLOCK Mgr
CKIN
AC
BD
I/V
RF ADC
SYNC d0 d1 d2 d3 d4 d5 d6/OF d7/UF Output MUX
E
I/V
F
I/V
Servo ADC
Control I/F
SDA SCL
Laser Driver
LD MD
Stereo DAC
MUTEL MUTER DL DR
OUTL OUTR
1.0 HARDWARE DESCRIPTION 1.1 Clock source and generation The master clock to operate the device is 768 xFs (High Frequency mode, HFM) or 384 xFs (Low Frequency mode, LFM). Fs=44.1KHz for CD applications. In either case, the clock is generated by TDA7522: an internal low-jitter Charge-Pump PLL (CPPLL) and a Finite State Machine (FSM) synthesize all the needed clocks for the internal blocks: a 512 xFs for the DAC and three 384 xFs (HFM) or 192xFs (LFM), with different phases for ADCs and output digital multiplexer. The required loop filter network is made up of a 160pF capacitor from FILT to GND_pll in parallel with the series of a 10nF and a 4K resistor. All clock related setups are communicated to TDA7521 via UART interface. 1.2 Voltage references REFIN is an internal voltage reference generated by a resistor divider between VCC_dac and VSS_dac. Nominal value (with VCC_dac=5V) is REFIN=2.5V. Careful filtering of this pin is essential; recommended value of external capacitor is 47 paralleled with 100nF ceramic. REFOUT is a 2.5V (nominal) buffered F output to bias the pickup. All the internal voltage references for ADCs and DACs are generated by bandgap-based circuits, thus allowing to reduce the noise induced by the power supply.
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1.3 Laser driver section The laser driver system is composed by the pick-up, the laser driver and the external PNP bipolar transistor. It controls the external pick-up current level (up to 100mA) through its base current in order to maintain a certain amount of diode power emission, independently from temperature and aging effects. This is done in a digital way by using a 6-bit DAC to set the monitor diode analog reference voltage at a constant level (and so the current in the laser diode). Thus, 26-1 different bias currents (with relative monitor voltage between 100 and 300mV) can be selected via UART interface. A negative feedback loop sets both the monitor diode voltage and the laser diode bias current. 1.4 Preamplifier section The goal of this section is to free the four voltage signals coming from either the CD pickup itself (voltage inputs) or the internal current-to-voltage converters (current inputs) from their intrinsic DC component and to amplify them to a level suitable for efficient A/D conversion. In case of current inputs, four transimpedance amplifiers convert the currents from AC (A+C), BD (B+D), E and F inputs into output voltages suitable for the programmable preamplification chain; otherwise, this stage is by-passed and the voltage inputs are directly connected to the preamplification stage. The two paths (for input current or input voltage) are digitally selected via UART interface. In the same way also the gain of the path and the offset cancellation for the preamplification chain are controlled (the gain programmability range is spanning from 6 up to 29.5dB in 48 discrete steps of 0.5dB each, while the offset nulling circuit allows a minimum correction step of about 22mV via a 6-bit DAC). Moreover the preamplification chain generates an HF signal, which carries the encoded audio data and is obtained by combining the photo-detector outputs as A+B+C+D. All these signals (AC, BD, E, F and HF), which can be evaluated by means of the monitor output, are fed to the ADC section. 1.5 ADC section The HF and servo (AC, BD, E and F) paths are digitized by means of two ADCs: the former (8-bit resolux tion, interleaved comparator two step architecture) samples the HF signal at a frequency of 384Fs (HFM) or 192xFs (LFM), the latter (6-bit resolution, interleaved comparator two step architecture) allows to multiplex the data for the servo path (AC, BD, E and F) in an only analog signal AC/BD/E/F and samples this signal at 384xFs (HFM) or 192xFs (LFM); that means each servo signal is sampled at 96 xFs or 48xFs). Then both the bitstreams (HF and AC/BD/E/F) are digitally multiplexed in a single bitstream (AC/HF/BD/ HF/E/HF/F/HF). A SYNC signal (high during the period of HF before AC output) is provided in order to point out the start of a new frame. It is worth noting that output data change on the falling edge of the master clock. The Table 1 shows the output data format for the ADC section: referring to AC/HF/BD/HF/E/ HF/F, the HF signal have an 8-bit format which represents the digitized value of the HF analog signal while the data for , the servo path (AC, BD, E and F) have a different format:6 bit for the digitized value of the analog output from the preamplifiers plus underflow and overflow(1). Table 1. TDA7521 Output Format
LSB D0 D1 D2 D3 D4 D5 D6/UF MSB D7/OF
Note: 1. Overflow and Underflow for the HF ADC are latched by a dedicated FSM and read via UART interface.
1.6 DAC section In TDA7521 are present two 3rd order SC smoothing filters to be used in Digital-to-Analog conversion. Its input signal is a bitstream created by a 2nd order digital modulator present in TDA7522. From there
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the bitstream is passed to the analog chip and properly processed by the filter. The filter exhibits 96dB SNR and more than -80dB THD for a full scale input signal.
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Figure 2. TDA7521 timings in 768xFs mode
(1 (2 (3.A) (3.B) (3.C) (3.D) AC BD RF RF
R B
BD E RF RF
R E
E F RF RF
R F
F AC RF RF
R A
AC BD RF RF
R B
BD E RF RF
R E
E F RF RF
R F
F
(4 (5
RF RF
R
(6 (7 (8
R
A
R
B
R
E
R
F
R
A
R
B
R
E
R
F
(9
(10)
(11)
(12.A) (12.B) (12.C)
Fig.3.
A349 timing: (1) External clock ( 768x FS mode); (2) Servo clock (servo data change on its rising edge, while RF data change on the falling edge); (3.A, 3.B, 3.C, 3.D) Internally generated 96 x FS clocks for Servo ADC; (4) Servo data IN; (5) Servo data OUT; (6) RF data IN; (7) RF data OUT; (8) AC/RF/BD/RF/E/RF/F/RF data stream before digital MUX; (9) Output AC/RF/BD/RF/E/RF/F/RF; (10) Synthesized clock; (11) Generic Bitstream Input; (12.A, 12.B, 12.C) Possible synthesized 256x FS (depending on the initial conditions)
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2.0 FEATURE The main performance of TDA7521 are reported below Table 2. Main DC Characteristics (I)
Current input A+C diode input B+D diode input E diode input F diode input Condition Min 1 1 1 1 Typ Max 16 16 16 16 Unit A A A A
Table 3. Main DC Characteristics (II)
Voltage input A+C diode input B+D diode input E diode input F diode input Conditi on Min 45 45 45 45 Typ Max 700 700 700 700 Unit mVpp mVpp mVpp mVpp
The polarity of input signals can be defined by ST7 individually Table 4. AC Main Performances
Contents DC offset range of each diode signals Frequency Range Group delay Flatness SNR Individual Gain Adjustment on AC, BD, E, F Gain Step range Individual Offset Adjustment on AC, BD, E, F MD (Monitor Diode) voltage range MD Adjustment Step 100 5 300 mV mV 48 0 0.5 23.5 Conditio n (*) Max input P-P Min 0 DC Typ Max 3/2 (*) 4M 4 Unit mVpp MHz nsec dB dB dB
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Table 5. AC Main Performances
DAC Single end Output Frequency response Dynamic Range THD@Full scale Condition VCC/2 DC 20 96 -80 Min Typ Max 1 22K Unit Vrms Hz dB dB
3.0 PIN FUNCTION TDA7521 is housed in a 44 quad flat pack package; the related pin list is reported below. Table 6. TDA7521 Pin List
Pin Number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Name AC BD E F REXT REFOUT REFIN MUTER MUTEL PON OUTR VSS_DAC OUTL VCC_DAC VDD_DAC GND_DAC Vss,DAC_Ref Vcc,DAC_Ref VDD_PLL FILT GND_PLL CKIN BSL Vdd I/O Gnd I I Pin I I I I I O I I I I O Gnd O Vdd Vdd Gnd Description A+C diode current input / voltage input DC coupled (1) B+D diode current input / voltage input DC coupled (1) E diode current input / voltage input DC coupled (1) F diode current input / voltage input DC coupled (1) External Reference resistor (2) Output Reference Voltage (5) VCC/2 Reference Voltage (4) Right Audio Channel Mute (6) Left Audio Channel Mute (6) Power shutdown / Reset (7) Right Audio Channel Analog output (8) DAC Analog Ground Left Audio Channel Analog output (8) DAC Analog Supply (5V) DAC Digital Supply (5V) DAC Digital Ground (3) (3) PLL 5V Supply PLL Loop Filter (9) PLL Ground Master clock input Digital Bit Stream input, Left Channel
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Pin Number 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name BSR SYNC D7 D6 D5 D4 D3 D2 D1/UF D0/OF GND_ADC VDD_ADC GND_ADC VCC_ADC SCK SDA HFMON LD MD VSS_PRE VCC_PRE Pin I O O O O O O O O O Gnd Vdd Gnd Vdd I I/O O O I Gnd Vdd Description Digital Bit Stream input, Right Channel ADC Mux Sync output (10) ADC output [MSB] ADC output ADC output ADC output ADC output ADC output (11) (12) ADC Ground ADC 5V Supply ADC Ground ADC 5V Supply ST7 Control I/F Clock input ST7 Control I/F Data (14) HF output (13) Laser Control output (15) Monitor diode input Pre_AMP Ground Pre_AMP 5V Supply
Notes: 1. Current or Voltage input, DC coupled 2. Precision Resistor connected between Rext and ground 3. These pins are to be left unconnected 4. Internally generated, need external filter ing cap 5. Buffered Vcc/2 Output 6. Driven by IC6D, active high 7. Dirven by IC6D, active low 8. 1 Vrms max., VCC/2 DC component 9. Needs RC-C externals network 10.High in correspondence of the HF sample preceding the AC one 11.LSB+1 of the HF ADC, Underflow bit of the servo one 12.LSB of the HF ADC, Overflow bit of the servo one 13.Can be selected among HF, AC, BD, E, F (via control interface) 14.Bidirectional, needs a pull-up resistor to 5 V line 15.Drives an external pnp.
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4.0 TDA7521 REGISTERS ADDRESS MAP Inside TDA7521 there are 16 registers that are to programmed by TDA7522; table nr.9 report the list. All registers are 8 bit wide. Table 7. TDA7521 registers Map
Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AC Gain reg BD Gain reg E Gain reg F Gain reg AC Offset Adjustment reg BD Offset Adjustment reg E Offset Adjustment reg F Offset Adjustment reg Monitor Output reg Laser Driver reg PLL reg Overflow reg (read only) Test mode register --unused-Every Gain reg * Every Offset reg * Register
Note: 1. With these two configuration the data sent to the slave section is written inside every Gain/Offset register. This function can thus be used to have a quick and global programming of the afore said register.
.
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TQFP44 - 44 lead Quad Flat Package
mm Min 0.05 1.35 0.30 0.09 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.45 0 0.60 1.00 3.5 7 0 0.75 0.018 1.40 0.37 Typ Max 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 3.5 7 0.030 0.055 0.014 Min inch Typ Max 0.063 0.006 0.057 0.018 0.008
Symb A A1 A2 B C D D1 D3 e E E1 E3 L L1 k
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B C L K
e
TQFP4410
Drawing is not to scale.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express writt en approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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